Apparatus for Memory Interface Configuration and Associated Methods

ABSTRACT

An apparatus includes a memory circuit and an interface circuit. The interface circuit is coupled to the memory circuit. The interface circuit selects a phase value of clock signal adapted to clock the memory circuit.

TECHNICAL FIELD

The disclosed concepts relate generally to memory devices or circuitsand, more particularly, to apparatus for configuring memory interfacedevices and circuits, and associated methods.

BACKGROUND

Electronic circuitry generally, and integrated circuits (ICs) inparticular, have continuously increased in complexity. For example,system-on-a-chip (SoC) devices include a relatively large number ofcircuits and devices on one IC. One type of circuitry widely used inelectronic ICs is memory circuits. Sometimes, the memory circuit uses agiven or desired protocol for communication with other circuitry. Theprotocol typically includes specification for a number of parameters,for example, clock signals, timing of various signals, and the like.

SUMMARY

The disclosed concepts relate generally to memory devices or circuitsand, more particularly, to configuring memory interface devices andcircuits. One aspect of the disclosed concepts relates to apparatus forconfiguring memory devices and circuits. In one exemplary embodiment, anapparatus includes a memory circuit, and an interface circuit. Theinterface circuit is coupled to the memory circuit. The interfacecircuit selects a phase value of a clock signal adapted to clock thememory circuit.

In another exemplary embodiment, an IC includes a memory circuit, and aninterface circuit. The interface circuit is coupled to the memorycircuit. The interface circuit provides a clock signal to the memorycircuit. The interface circuit includes a shift register that sweeps orchanges a phase of the clock signal to select a phase value appropriatefor interfacing with the memory circuit.

Another aspect of the disclosed concepts relates to methods ofconfiguring memory devices and circuits. In one exemplary embodiment, amethod of operating a memory includes selecting a phase value of a clocksignal adapted to clock the memory circuit during a data captureoperation. The phase value of the clock signal is selected such that theresults of the data capture operation meet a specified criterion.

BRIEF DESCRIPTION OF THE DRAWINGS

The appended drawings illustrate only exemplary embodiments andtherefore should not be considered as limiting its scope. Persons ofordinary skill in the art who have the benefit of this disclosureappreciate that the disclosed concepts lend themselves to other equallyeffective embodiments. In the drawings, the same numeral designatorsused in more than one drawing denote the same, similar, or equivalentfunctionality, components, or blocks.

FIG. 1 depicts a simplified general block diagram of an integratedcircuit according to an exemplary embodiment.

FIG. 2 illustrates a general block diagram of a programmable logicdevice (PLD) according to an exemplary embodiment

FIG. 3 shows a mechanism for generating clock signals with appropriatephases according to an exemplary embodiment.

FIG. 4 depicts a simplified flow diagram for selecting or calculatingsettings for a memory circuit or device according to an exemplaryembodiment.

FIG. 5 illustrates a data capture scheme according to an exemplaryembodiment.

FIG. 6 depicts another data capture scheme according to an exemplaryembodiment.

FIG. 7 illustrates a circuit according to an exemplary embodiment forsweeping or changing phase values.

FIG. 8 shows a simplified flow diagram for some of the operations of thecircuit in FIG. 7.

DETAILED DESCRIPTION

The disclosed concepts relate generally to memory devices or circuits.More specifically, the disclosed concepts provide apparatus and methodsfor configuring or calculating settings for memory devices, circuits,and/or interfaces, for example, the clock rate or signal used to clockthe memory-related circuitry. One may perform the configuration orcalculation of the settings as part of a calibration mechanism, asdesired.

The disclosed concepts provide a mechanism for calculating a pluralityof settings used by circuitry within an IC or physical layer or circuit(PHY) to communicate with memory devices or circuits via a given ordesired interface. Furthermore, as persons of ordinary skill in the artwho have the benefit of the description of the disclosed conceptsunderstand, one may also apply the disclosed concepts to memory externalto the IC. In this scenario, the memory communicates with the IC via anappropriate mechanism, such as an interface circuit, input/output (I/O)circuitry, and the like.

One may apply the disclosed concepts to circuitry or systems that use arelatively wide variety of types of memory. Examples of memory devicesor circuits include double data rate (DDR) memory, for example, DDR2 orDDR3 (generally, DDRn), and Reduced Latency Dynamic Random Access Memory(RLDRAM). More generally, one may apply the disclosed concepts to anyinterface that returns a source synchronous clock, and uses adestination synchronous clock to resynchronize it to an internal clockdomain. As persons of ordinary skill in the art who have the benefit ofthe description of the disclosed concepts understand, however, one mayuse the disclosed concepts in conjunction with other types of memory, asdesired.

Using apparatus and techniques according to the disclosed conceptsprovides several benefits. First, it allows simplifying the calculationlogic or circuit for the memory settings. Second, it reduces the sizeand complexity of the memory interface circuits used. Third, it allowsintellectual property (IP) re-use within the PHY for many functions(depending on calibration complexity) and, because of its design, it nolonger presents a frequency bottleneck within the PHY. Fourth, itaccommodates changes in clock frequency in various designs andimplementations, and enables higher speed operation of the PHY andhigher bandwidth memory interfaces. Fifth, it provides a calculationmechanism for DDR de-skew, write leveling, resynch (resynchronization)and post-amble.

Conceptually, one aspect of the disclosed concepts provides mechanismsand techniques for proper selection of a phase for a clock signal. Theclock signal, when used to interface with a memory device or circuit,allows proper communication of the memory device or circuit, whileallowing relatively high (or higher) bandwidth memory interfaces. Inother words, the disclosed concepts provide a way of dynamicallydetermining the clock phase for appropriate functioning of the memoryand the memory interface.

FIG. 1 illustrates a simplified general block diagram of an IC 100according to an exemplary embodiment. IC 100 may constitute a widevariety of ICs. Examples include general-purpose and special-purposeICs, application specific ICs (ASICs), and the like, including stackeddie and stacked packages.

IC 100 includes memory 124 (one or more memory devices or circuits), andcontroller/interface circuit 127. In addition, IC 100 includes ICcircuitry 102.

As noted above, memory 124 may constitute a variety of desired memorytypes/circuits. Generally speaking, IC circuitry 102 may include a widevariety of circuitry that read data from and/or write data to, memory124. Examples include registers, general logic circuits, processors,arithmetic/logic circuits, and the like.

Controller/interface circuit 127 provides a mechanism for communicationbetween memory 124 and IC circuitry 102. Through controller/interfacecircuit 127, IC circuitry 102 can read data from and/or write data to,memory 124. As described in detail below, controller/interface circuit127 includes a mechanism for changing a phase of a clock signal used tocommunicate with memory 124 in order to find the appropriate phase thatprovides reliable and relatively high-bandwidth communication withmemory 124.

As noted above, one may apply the disclosed concepts to a variety ofcircuits and systems, including a variety of ICs. One example of such anIC constitutes a programmable logic device (PLD).

FIG. 2 illustrates a general block diagram of a PLD 103 according to anexemplary embodiment. As described in detail below, similar to IC 100(see FIG. 1), PLD 103 includes memory 124 and controller/interfacecircuit 127. Memory 124 and controller/interface circuit may havesimilar structure and functionality as described above.

PLD 103 includes configuration circuitry 130, configuration memory(CRAM) 133, control circuitry 136, programmable logic 106, programmableinterconnect 109, and I/O circuitry 112. In addition, PLD 103 mayinclude test/debug circuitry 115, one or more processors 118, one ormore communication circuitry 121, one or more memories 124, one or morecontrollers 127, and initialization circuit 139, as desired.

Note that the figure shows a simplified block diagram of PLD 103. Thus,PLD 103 may include other blocks and circuitry, as persons of ordinaryskill in the art understand. Examples of such circuitry include clockgeneration and distribution circuits, redundancy circuits, and the like.Furthermore, PLD 103 may include, analog circuitry, other digitalcircuitry, and/or mixed-mode circuitry, as desired.

Programmable logic 106 includes blocks of configurable or programmablelogic circuitry, such as look-up tables (LUTs), product-term logic,multiplexers (MUXs), logic gates, registers, memory, and the like.Programmable interconnect 109 couples to programmable logic 106 andprovides configurable interconnects (coupling mechanisms) betweenvarious blocks within programmable logic 106 and other circuitry withinor outside PLD 103.

Control circuitry 136 controls various operations within PLD 103. Underthe supervision of control circuitry 136, PLD configuration circuitry130 uses configuration data (which it obtains from an external source,such as a storage device, a host, etc.) to program or configure thefunctionality of PLD 103. Configuration data are typically stored inCRAM 133. The contents of CRAM 133 determine the functionality ofvarious blocks of PLD 103, such as programmable logic 106 andprogrammable interconnect 109. Initialization circuit 139 may cause theperformance of various functions at reset or power-up of PLD 103.

I/O circuitry 112 may constitute a wide variety of I/O devices orcircuits, as persons of ordinary skill in the art who have the benefitof the disclosure understand. I/O circuitry 112 may couple to variousparts of PLD 103, for example, programmable logic 106 and programmableinterconnect 109. I/O circuitry 112 provides a mechanism and circuitryfor various blocks within PLD 103 to communicate with external circuitryor devices. As noted, in some embodiments, I/O circuitry 112 may providea mechanism for communication with memory external to PLD 103.

Test/debug circuitry 115 facilitates the testing and troubleshooting ofvarious blocks and circuits within PLD 103. Test/debug circuitry 115 mayinclude a variety of blocks or circuits known to persons of ordinaryskill in the art who have the benefit of the disclosure. For example,test/debug circuitry 115 may include circuits for performing tests afterPLD 103 powers up or resets, as desired. Test/debug circuitry 115 mayalso include coding and parity circuits, as desired.

PLD 103 may include one or more processors 118. Processor 118 may coupleto other blocks and circuits within PLD 103. Processor 118 may receivedata and information from circuits within or external to PLD 103 andprocess the information in a wide variety of ways, as persons skilled inthe art with the benefit of the disclosure in this document appreciate.One or more of processor(s) 118 may constitute a digital signalprocessor (DSP). DSPs allow performing a wide variety of signalprocessing tasks, such as compression, decompression, audio processing,video processing, filtering, and the like, as desired.

PLD 103 may also include one or more communication circuits 121.Communication circuit(s) 121 may facilitate data and informationexchange between various circuits within PLD 103 and circuits externalto PLD 103, as persons of ordinary skill in the art who have the benefitof the disclosure in this document understand.

PLD 103 may further include one or more memories 124 and one or morecontroller/interface circuits 127. Memory 124 allows the storage ofvarious data and information (such as user-data, intermediate results,calculation results, etc.) within PLD 103. Memory 124 may have agranular or block form, as desired. Controller/interface circuit 127allows interfacing to, and communicating with memory 124.

As noted above, in various embodiments (IC 100 generally or PLD 103), aphase of a clock signal is varied in order to find an appropriate oroptimal clock phase for proper communication with memory 124. The clockphase is then used to interface with memory 124.

FIG. 3 shows a mechanism for generating clock signals with appropriatephases according to an exemplary embodiment. IC 100 (or PLD 103)includes signal generator 203, and phase locked loop (PLL) 209. Signalgenerator 203 generates an output signal 206, which it provides to PLL209. Output signal 206 may constitute a clock signal. As persons ofordinary skill in the art who have the benefit of the description of thedisclosed concepts understand, signal generator 203 may constitute anI/O pin on IC 100 or PLD 103, or another structure in the device, forinstance, programmable interconnect 109 in PLD 103, or a signal fromanother PLL.

PLL 209 uses output signal 206 of signal generator 203 as an inputsignal in order to generate PLL signal 212. The operation and structureof PLL 209 is known to persons of ordinary skill in the art.

PLL 209 provides PLL signal 212 to controller/interface circuit 127. PLLsignal 212 may constitute a clock signal or signals, as desired,depending on a given implementation or given specifications.Controller/interface circuit 127 may use PLL signal 212 or one or moresignals 218, derived from PLL signal 212 (e.g., by frequency division),to interface or clock memory 124 (not shown explicitly).

Generally, PLL 209 may change the phase and/or frequency of PLL signal212. Controller/interface circuit 127 uses one or more signals 215 tocause PLL 209 to change the phase and/or frequency of PLL signal 212.

In various exemplary embodiments, controller/interface circuit 127attempts communicating with (e.g., clocking, interfacing, transferringdata) memory 124 (not shown explicitly) using PLL signal 212 (or signal218). Controller/interface circuit 127 keeps track of and recordsinformation about the results of the communication with memory 124. Forexample, controller/interface circuit 127 may record or store whetherthe communication succeeded, the phase of PLL signal 212, etc.

Controller/interface circuit 127 uses signal(s) 215 to cause PLL 209 tochange the phase of PLL signal 212. In exemplary embodiments,controller/interface circuit 127 causes (through signal(s) 215) PLL 209to sweep or change (one or more times) the phase of PLL signal 212through a range of phase values, using given or desired phaseincrements. By sweeping through a range of phase values, or changing thephase value, one may evaluate the performance of the interface withmemory 124 and the performance of memory 124 (e.g., data transfer rate,transfer reliability, etc.).

As noted, the phase change sweep may occur using desired increments.Furthermore, the phase change sweep may occur over any desired range(s)of phase values. For example, the phase change sweep may occur over a360-degree range in some exemplary embodiments, and over a 720-degreerange in some other exemplary embodiments. Generally, the phase changeor sweep may occur over an (M*360)-degree range of phase values, where Mdenotes an integer.

At each phase value, controller/interface circuit 127 keeps track of andrecords information about the results of the communication with memory124. As noted above, controller/interface circuit 127 may, for example,record or store whether the communication succeeded, the phase of PLLsignal 212, etc.

At the conclusion of the phase change or sweep, controller/interfacecircuit 127 can select the phase value that provides proper operation ofmemory 124 and interface and communication with memory 124. For example,controller/interface circuit 127 may determine which phase value orphase windows (including, as desired, the start, end, and center valuesfor the windows) would result in reliable or robust data transfer to andfrom memory 124. As another example, controller/interface circuit 127may determine which phase value or phase windows (including, as desired,the start, end, and center values for the windows) would result in thehighest speed of operation and data transfer to and from memory 124.

As persons of ordinary skill in the art who have the benefit of thedescription of the disclosed concepts understand, one may use othercriteria for selecting a phase value in addition to, or instead of, thecriteria described above. For example, one may select a phase value sothat operation of memory 124 and/or and communication to and from memory124 satisfy a given margin of safety, e.g., one or more margins forvarious signal or event timing values.

Regardless of the criterion (or a combination of criteria, as desired),controller/interface circuit 127 may select a phase value andcommunicate that phase value to PLL 209 (via signal(s) 215). PLL 209 maythen generate PLL signal 212 with that phase value.

In addition to selecting a phase value, one may also periodically adjustor calibrate the phase value based on changes in temperature, voltage,and the like. Specifically, the performance of practical circuits variesas a function of temperature and voltage or current levels. Thus, overtime, a static phase value may not provide optimal or proper circuitoperation.

Accordingly, in exemplary embodiments, controller/interface circuit 127may periodically adjust the phase value used by PLL 209 in response tochanges in voltage, temperature, current, etc., or a combination ofthose factors. One may implement such functionality by using sensorsthat sense values of the parameter(s) (e.g., voltage, temperature,etc.), and a circuit that translates the sensed value(s) to changes inthe phase value (e.g., a look-up table).

FIG. 4 depicts a simplified flow diagram for selecting or calculatingsettings for operation of a memory circuit or device according to givenor desired specifications or criteria. At 303, a phase change or sweepis performed. As noted above, the phase change or sweep may occur with adesired phase increment and over a desired phase range.

For each phase value in the phase range, at 306 data are allowed topropagate to and/or from memory device(s) or circuit(s). At 309, adetermination is made whether data captured from the memory device(s) orcircuit(s) meet one or more specified or desired criteria (e.g., whetherthe data are “good”).

At 312, the results of the determination at 309 are stored or recorded.At 315, a determination is made whether all phases and data pins orlines to be tested have been tested. If so, a phase value issubsequently selected. If not, the phase change or sweep continues at303.

In exemplary embodiments, the selected phase value may be periodicallyadjusted in response to changes in voltage, temperature, current, etc.,or a combination of those factors. The periodic adjustment provides away of correcting or optimizing the phase value based on environmentalor operational characteristics of the circuit.

As noted above, one may use the disclosed concepts with DDR memory. Inthis application, one may use DQS-based data capture, or calibratedcapture clock to transfer data to and from memory. FIGS. 5 and 6illustrate those two data capture schemes, respectively.

Referring to FIG. 5, registers 406A-406C constitute data captureregisters. The input data are provided to capture registers 406A-406Cvia delay circuit 403. A strobe clock signal 418 clocks registers406A-406C. Specifically, clock signal 418 couples to register 406A,whereas the inverted version of clock signal 418 (produced by inverter409) couples to registers 406B-406C.

The output of registers 406B-406C drive the data inputs of resynch(resynchronization) registers 412A-412C. Registers 412A-412C provide theoutput data. The output data may be provided to other circuitry, such asIC circuitry 102 (see FIG. 1), or circuitry within PLD 103 (see FIG. 2),etc.

Resynch clock signal 415 serves as the clock signal for registers412A-412C. Resynch clock signal 415 constitutes output signal 218 (notshown explicitly) of controller/interface circuit 127 (not shownexplicitly), PLL signal 212 (not shown explicitly), or a signal derivedfrom one of those signals. Thus, resynch clock signal 415 is calibratedin the circuit shown in FIG. 5.

In contrast, in the circuit of FIG. 6, the capture clock signal iscalibrated. Referring to FIG. 6, the input data are provided toregisters 503 and 506A. The output of register 503 drives the data inputof register 506B. Registers 506A-506B provide the output data. Theoutput data may be provided to other circuitry, such as IC circuitry 102(see FIG. 1), or circuitry within PLD 103 (see FIG. 2), etc.

Capture clock signal 509 serves as the clock signal for register 503 andregisters 506A-506B. Capture clock signal 509 constitutes output signal218 (not shown explicitly) of controller/interface circuit 127 (notshown explicitly), PLL signal 212 (not shown explicitly), or a signalderived from one of those signals. Thus, capture clock signal 509 iscalibrated in the circuit shown in FIG. 6.

One aspect of the disclosed circuits relates to circuitry fordetermining the optimal, desired, or proper phase value by changing orsweeping phase values. In exemplary embodiments, one may use a shiftregister to implement that functionality.

FIG. 7 a shift-register-based circuit according to an exemplaryembodiment for changing or sweeping phase values. The circuit in FIG. 7includes multiplexers (MUXs) 603, 606, and 609; registers 620A-620I,register 612, and processing logic circuit 615.

Registers 620A-620I form a shift register. Thus, the Q output ofregister 620A couples to the data (D) input of register 620B, and so on(including the selective coupling provided by MUXs 603, 606, and 609).

Processing logic circuit 615 constitutes a controller for the circuit inFIG. 7. One may implement processing logic circuit 615 in a variety ofways, as persons of ordinary skill in the art who have the benefit ofthe description of the disclosed concepts understand. For example, insome exemplary embodiments, one may use a finite state machine (FSM). Asanother example, in some illustrative embodiments, one may use amicrocontroller, or a microprocessor or, generally, a processor.

In the embodiment shown, one may select to serially load the shiftregister or use vector sizes of 5, 7, or 9 for the shift register byusing MUXs 603, 606, and 609. Put another way, MUXs 603, 606, and 609,under the control of processing logic circuit 615, provide a mechanismfor changing the length of the shift register when acting as a barrelshifter.

As shown in FIG. 7, processing logic circuit 615 controls the select (S)inputs of MUXs 603, 606, and 609. One input to MUXs 603, 606, and 609constitutes the output signal of register 620I (the last register in theshift register). A second input of MUX 603 constitutes the input data. Asecond input of MUX 606 constitutes the output of register 620B, whereasa second input of MUX 609 constitutes the output of register 620D.

As noted, one may use MUXs 603, 606, and 609 to select a desired vectorsize. For example, to select a vector size of 7, one causes (viaprocessing logic circuit 615) MUX 606 to couple the output of register620I to the input of register 620C, and MUX 609 to couple the output ofregister 620D to the input of register 620E.

In similar fashion, one may select vector sizes of 5 or 9. To select avector size of 5, one causes (via processing logic circuit 615) MUX 609to couple the output of register 620I to the input of register 620E.Generally speaking, as persons of ordinary skill in the art who have thebenefit of the description of the disclosed concepts understand, one mayuse the disclosed concepts to a wide variety of vector sizes, by makingappropriate modifications to the circuitry and techniques shown anddescribed.

To load data into the shift register, MUX 603 (under control ofprocessing logic 615) passes data from the data input to register 620A.MUX 606 and 609 pass the data through the scan chain, i.e., fromregister 620B to register 620C, and from register 620D to register 620E,respectively. When all the bits have been shifted into the shiftregister (registers 620A-620I), then the vector may be shifted to copewith a vector of smaller then 9 and get the first bit into register620I, as desired.

As persons of ordinary skill in the art who have the benefit of thedescription of the disclosed concepts understand, one may apply manymodifications and tweaks to the disclosed concepts, circuits, andtechniques that can cover processing the data to detect the largestgroup of ones (binary 1s) in a linear window. Other modifications, likeadding a padding of binary 0 as the last bit of data loaded can simplifysuch tasks. Indeed, for some edge detection conditions like ‘lastfailing phase,’ a signal from the output of register 620K can be useful.

Thus, the embodiment shown in FIG. 7 supports a serial-loading shiftregister with vector sizes of 5, 7, and 9. For vector sizes of 5, 7 and9, the circuit uses a circular window. Note, however, that one may useother vector sizes, as desired, by making modifications that fall withinthe level of skill of persons of ordinary skill in the art who have thebenefit of the description of the disclosed concepts. The choice ofcircular versus linear window is made through the processing logiccircuit 615 (e.g., an FSM), which determines the maximum number ofshifts.

Furthermore, one may use a parallel-loading shift register, as desired.The parallel-loading shift register may have desired vector sizes. Onemay implement such options by making modifications to the circuit inFIG. 7 that fall within the level of skill of persons of ordinary skillin the art who have the benefit of the description of the disclosedconcepts.

Typically, a range of valid phase values exist for a given circuit andoperating conditions. One may consider the range of phase values awindow. The circuit in FIG. 7 operates by finding the center of largestwindow of phase values that produce valid captured data. One bit in eachstage of the shift register represents pass or fail for that setting ofphase value.

With the aid of the shift register, processing logic 615 evaluates arange of phase values over a set of windows. The windows may indicatethat use of a particular phase value or range of phase values results ina pass condition (i.e., proper data capture to/from the memory) or afail condition (i.e., faulty or improper data capture to/from thememory). As persons of ordinary skill in the art who have the benefit ofthe description of the disclosed concepts understand, fringing effectsof unstable pass/fail conditions on the interface being calibrated maymanifest themselves as multiple windows.

The shift register forms a barrel shifter. As noted above, the data areshifted serially around the barrel shifter. During this process,processing logic circuit 615 detects the start or end of a window using0-to-1 and 1-to-0 transitions.

Start and end conditions of a window are used to calculate their start,size, and center values. Register 612 holds the value which was shiftedout of register 620I. Doing so minimizes the comparison logic, asotherwise the previous value which was in register 620I would have to beread from register 620A, 620C, or 620E depending on the length of vectorselected

As noted, one may program the shift register to perform the aboveoperations over a circular window (barrel shifting) or a linear range.This property allows performing edge detection (rising or fallingedges), which may be used for write leveling, post-amble, and or de-skewcalculations during calibration, as persons of ordinary skill in the artwho have the benefit of the description of the disclosed conceptsunderstand.

In addition, the shift register may be programmed to operate as a linearwindow over N+1 bits. if the (N+1)th bit is forced to binary zero as itis loaded, then one will find a valid window of phase values. Forexample, a 6 bit linear window may be loaded into the vector length 7,padded with a zero (fail). When processed as a circular window, thepadding bit(s) cause the circuit to see the window of the desired sizeand force the result into the appropriate range. One may use thisattribute for de-skew calculations, as persons of ordinary skill in theart who have the benefit of the description of the disclosed conceptsunderstand.

Note that one may dynamically (on the fly) select a vector size, i.e.,the register in the shift register into which the output of the lastregister if fed. This attribute allows using one circuit at differentclock frequencies, as different clock frequencies may mandate adifferent number of phase steps per clock cycle, hence a differentvector size. An example constitutes structured ASIC products, such asHardCopy devices provided by Altera Corporation, the assignee of thispatent application. Choosing the maximum vector size limits the maximumnumber of phases available; however any setting that utilizes fewerphase steps would be supported. Furthermore, because of this attribute,one may use the same circuit for tracking and resynch calculation, aspersons of ordinary skill in the art who have the benefit of thedescription of the disclosed concepts understand.

Note that one may use a phase window of 360 degrees or 720 degrees, asdesired. For example, one may use a 360-degree window for non DQS-basedapplications (see FIG. 6), as persons of ordinary skill in the art whohave the benefit of the description of the disclosed conceptsunderstand. Conversely, one may use a 720-degree window for half-ratePHY applications or a DQS based capture scheme (see FIG. 5). Optionally,the results may be mapped into the first 360 degrees, as desired.

One may use merely one bit as a pass/fail flag for each phase value.Doing so results in circuitry with relatively small sizes, and alsoresults in relatively fast speeds of operation.

Furthermore, one may perform a logical operation on the results of phasewindow determination for a number of data bits or pins at the same pointin the shift register. By doing so, one may merge the results (i.e.,pass/fail windows) for each data pin or bit into one pass/fail windowfor the memory interface. For example, one may perform a logical ANDoperations on the results from different pins together to produce anaggregated value that once processed provides a result that will workfor all pins. This operation may be performed while loading the datainto the shift register (i.e., registers 620A-620I). Alternatively, onemay hold data from one pin and perform a logical AND with data from thenext pin before performing a shift operation.

Another option is to store all the phase results for one pin, and thenperform a logical AND operation on the value stored in the shiftregister with the value being loaded in. Other options for performinglogical operations exist, as persons of ordinary skill in the art whohave the benefit of the description of the disclosed conceptsunderstand.

In addition, note that one may use processing logic circuit to provide avariety of pass or fail information that depend on the type ofprocessing being performed. For example, one may indicate a failurecondition based on no binary 1s present (i.e., no passes), no binary 0spresent (no fails), multiple equally sized windows, etc. This abilityfacilitates debugging of the PHY and electrical interfaces, especiallyin more complex systems, such as DDR3.

FIG. 8 shows a simplified flow diagram for some of the operations of thecircuit in FIG. 7. At 703, a vector size is selected, and at 706, theshift register is configured accordingly.

At 709, a check is made to determine whether the processing hasfinished. If so, at 733, a determination is made whether an error hasoccurred and, if so, the error is recorded at 736.

If the processing has not finished, at 712 a determination is madewhether a start of a window is detected (e.g., a binary 1 value in theshift register 620I and binary 0 in register 612). If so, informationabout the start of the window is stored at 715. Also, if the start ofthe window is the first start condition encountered, then a flag is setto stop processing when this position is re-encountered in the shifteddata, thus forming one of the ‘done’ conditions at 709.

If a window start is not detected (e.g., a binary 0 value), at 718 adetermination is made whether a window end has occurred. If so, if thesize of the window is the largest so far encountered, that informationis stored at 721.

Otherwise, a determination is made at 724 whether the current bit of thewindow that is being examined is a binary 1. If so, at 727, the size ofthe window is incremented, and the center value of the window is updatedevery other cycle (i.e., via the divide-by-two operation). At 730, theshift register is shifted, and processing continues at 709.

As persons of ordinary skill in the art who have the benefit of thedescription of the disclosed concepts understand, one may apply thedisclosed concepts effectively to various ICs. Examples described inthis document (e.g., general purpose ICs, ASICs, PLDs) constitute merelyillustrative applications, and are not intended to limit the applicationof the disclosed concepts to other ICs by making appropriatemodifications. Those modifications fall within the knowledge and levelof skill of persons of ordinary skill in the art who have the benefit ofthe description of the disclosed concepts.

Referring to the figures, persons of ordinary skill in the art will notethat the various blocks shown might depict mainly the conceptualfunctions and signal flow. The actual circuit implementation might ormight not contain separately identifiable hardware for the variousfunctional blocks and might or might not use the particular circuitryshown. For example, one may combine the functionality of various blocksinto one circuit block, as desired. Furthermore, one may realize thefunctionality of a single block in several circuit blocks, as desired.The choice of circuit implementation depends on various factors, such asparticular design and performance specifications for a givenimplementation, as persons of ordinary skill in the art who have thebenefit of the description of this disclosure understand. Othermodifications and alternative embodiments in addition to those describedhere will be apparent to persons of ordinary skill in the art who havethe benefit of this disclosure. Accordingly, this description teachesthose skilled in the art the manner of carrying out the disclosedconcepts and are to be construed as illustrative only.

The forms and embodiments shown and described should be taken asillustrative embodiments. Persons skilled in the art may make variouschanges in the shape, size and arrangement of parts without departingfrom the scope of the disclosed concepts in this document. For example,persons skilled in the art may substitute equivalent elements for theelements illustrated and described here. Moreover, persons skilled inthe art who have the benefit of this disclosure may use certain featuresof the disclosed concepts independently of the use of other features,without departing from the scope of the disclosed concepts.

1-20. (canceled)
 21. A method of operating a memory, comprising clockingthe memory using a clock signal having a phase value; and changing thephase value of the clock signal adapted to clock the memory circuitduring a data capture operation such that the results of the datacapture operation meet a specified criterion.
 22. The method accordingto claim 21, wherein the specified criterion comprises the results ofthe data capture being valid.
 23. The method according to claim 21,wherein changing the phase value of the clock signal further comprisesselecting the phase value by evaluating a range of phase values using aset of windows.
 24. The method according to claim 23, wherein evaluatingthe range of phase values using the set of windows further comprisesevaluating each window in the set of windows to determine a passcondition or a fail condition.
 25. The method according to claim 21,wherein selecting the phase value of the clock signal further comprises:changing the phase value of the clock signal over a range of phasevalues; and capturing data for each phase value in the range of phasevalues.
 26. The method according to claim 25, further comprisingevaluating the data captured for each phase value in the range of phasevalues.
 27. The method according to claim 25, wherein changing the phasevalue of the clock signal is performed over a 360-degree range of phasevalues.
 28. The method according to claim 25, wherein changing the phasevalue of the clock signal is performed over a 720-degree range of phasevalues.
 29. An apparatus, comprising a memory clocked by a clock signalwith a phase value, wherein the phase value of the clock signal is sweptduring a data capture operation in order to results of the data captureoperation to meet a specified criterion.
 30. The apparatus according toclaim 29, wherein the phase value of the clock signal is swept over a360-degree range of phase values.
 31. The apparatus according to claim29, wherein the phase value of the clock signal is swept over a720-degree range of phase values.
 32. The apparatus according to claim29, wherein the phase value of the clock signal is swept over an(M*360)-degree range of phase values, where M is an integer.
 33. Theapparatus according to claim 29, further comprising a phase locked loop(PLL) adapted to generate an output signal from which the clock signalis derived.
 34. The apparatus according to claim 29, further comprisinga selectable vector size shift register that changes a phase of theclock signal to sweep the phase of the clock signal.
 35. The apparatusaccording to claim 34, wherein the shift register is serially loaded.36. The apparatus according to claim 34, wherein the shift register isloaded in parallel.
 37. The apparatus according to claim 34, wherein theshift register changes the phase of the clock signal by using a set ofwindows.
 38. The apparatus according to claim 37, wherein a window fromthe set of windows that has a largest size is selected.
 39. Theapparatus according to claim 29, wherein the data capture operationcomprises a DQS-based data capture operation.
 40. The apparatusaccording to claim 29, wherein the data capture operation comprises acalibrated capture clock data capture data capture operation.